Hitachi H8S/2628 Hardware Manual page 285

• TCSR_1 and TCSR_3
Initial
Bit Bit Name Value
7 CMFB 0
6 CMFA 0
5 OVF 0

4 1
3 OS3 0
2 OS2 0
R/W Description
R/(W)* Compare-Match Flag B
[Setting condition]
When TCNT = TCORB
[Clearing condition]
•
Read CMFB when CMFB = 1, then write 0 in
CMFB
•
DTC is activated by the CMIB interrupt and the
DISEL bit = 0 in MRB of DTC.
R/(W)* Compare-match Flag A
[Setting condition]
When TCNT = TCORA
[Clearing condition]
•
Read CMFA when CMFA = 1, then write 0 in
CMFA
•
DTC is activated by the CMIA interrupt and the
DISEL bit = 0 in MRB of DTC.
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF

Reserved
This bit is always read as 1 and cannot be modified.
R/W Output Select 3 and 2
R/W These bits specify how the timer output level is to be
changed by a compare-match B of TCORB and
TCNT.
00: No change when compare-match B occurs
01: 0 is output when compare-match B occurs
10: 1 is output when compare-match B occurs
11: Output is inverted when compare-match B occurs
(toggle output)
Rev. 1.0, 09/02, page 249 of 568