Hitachi H8S/2628 Hardware Manual page 23

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram .................................................................................................2
Figure 1.2 Pin Arrangement............................................................................................................3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode) .....................................................................13
Figure 2.2 Stack Structure in Normal Mode .................................................................................13
Figure 2.3 Exception Vector Table (Advanced Mode) .................................................................14
Figure 2.4 Stack Structure in Advanced Mode .............................................................................15
Figure 2.5 Memory Map ...............................................................................................................16
Figure 2.6 CPU Registers .............................................................................................................17
Figure 2.7 Usage of General Registers .........................................................................................18
Figure 2.8 Stack ............................................................................................................................19
Figure 2.9 General Register Data Formats (1) ..............................................................................22
Figure 2.9 General Register Data Formats (2) ..............................................................................23
Figure 2.10 Memory Data Formats...............................................................................................24
Figure 2.11 Instruction Formats (Examples) ................................................................................37
Figure 2.12 Branch Address Specification in Memory Indirect Mode .........................................41
Figure 2.13 State Transitions ........................................................................................................45
Section 3 MCU Operating Modes
Figure 3.1 Address Map................................................................................................................51
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)................................56
Figure 4.2 Reset Sequence
(Advanced Mode with On-chip ROM Disabled: Not Available in this LSI) ..............57
Figure 4.3 Stack Status after Exception Handling ........................................................................60
Figure 4.4 Operation when SP Value Is Odd................................................................................61
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ........................................................................64
Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5 ................................................................71
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0......77
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2.....................79
Figure 5.5 Interrupt Exception Handling ......................................................................................80
Figure 5.6 Conflict between Interrupt Generation and Disabling .................................................83
Section 6 PC Break Controller (PBC)
Figure 6.1 Block Diagram of PC Break Controller.......................................................................86
Rev. 1.0, 09/02, page xxi of xxxiv