Figure 4.1 Reset Sequence (Advanced Mode With On-Chip Rom Enabled) - Hitachi H8S/2628 Hardware Manual

φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction

Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)

Rev. 1.0, 09/02, page 56 of 568
Internal
Vector fetch
processing
(1) (3)
High
(2) (4)
Fetch of first
program instruction
(5)
(6)