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Table 10.13 TIORL_0 (Channel 0)
Bit 7
Bit 6
Bit 5
IOD3
IOD2
IOD1
0
0
0
1
1
0
1
1
0
0
1
1
X
Legend
X: Don't care
Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Description
Bit 4
TGRD_0
IOD0
Function
0
Output
compare
1
2
register*
0
1
0
1
0
1
0
Input
capture
2
register*
1
X
X
TIOCD0 Pin Function
Output disabled
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Capture input source is the TIOCD0 pin
Input capture at rising edge
Capture input source is the TIOCD0 pin
Input capture at falling edge
Capture input source is the TIOCD0 pin
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
Rev. 1.0, 09/02, page 175 of 568
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