Hitachi H8S/2628 Hardware Manual page 26

Figure 11.9 Timing of OVF Setting............................................................................................ 255
Figure 11.10 Conflict between TCNT Write and Clear .............................................................. 258
Figure 11.11 Conflict between TCNT Write and Increment ...................................................... 259
Figure 11.12 Conflict between TCOR Write and Compare-Match ............................................ 259
Section 12 Programmable Pulse Generator (PPG)
Figure 12.1 Block Diagram of PPG............................................................................................ 264
Figure 12.2 PPG Output Operation............................................................................................. 272
Figure 12.3 Timing of Transfer and Output of NDR Contents (Example) ................................. 273
Figure 12.4 Setup Procedure for Normal Pulse Output (Example)............................................. 274
Figure 12.5 Normal Pulse Output Example (Five-Phase Pulse Output) ..................................... 275
Figure 12.6 Non-Overlapping Pulse Output ............................................................................... 276
Figure 12.7 Non-Overlapping Operation and NDR Write Timing ............................................. 277
Figure 12.8 Setup Procedure for Non-Overlapping Pulse Output (Example)............................. 278
Figure 12.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)................ 279
Figure 12.10 Inverted Pulse Output (Example) .......................................................................... 281
Figure 12.11 Pulse Output Triggered by Input Capture (Example) ............................................ 282
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of WDT .......................................................................................... 283
Figure 13.2 Example of WDT0 Watchdog Timer Operation ..................................................... 287
Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)............................... 289
Figure 13.4 Conflict between TCNT Write and Increment ........................................................ 289
Section 14 Serial Communication Interface (SCI)
Figure 14.1 Block Diagram of SCI ............................................................................................. 292
Figure 14.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) .................................................. 315
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 317
Figure 14.4 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) ............................................................................................. 318
Figure 14.5 Sample SCI Initialization Flowchart ....................................................................... 319
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 320
Figure 14.7 Sample Serial Transmission Flowchart ................................................................... 321
Figure 14.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 322
Figure 14.9 Sample Serial Reception Data Flowchart (1) .......................................................... 324
Figure 14.9 Sample Serial Reception Data Flowchart (2) .......................................................... 325
Figure 14.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 327
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 328
Figure 14.12 Example of SCI Operation in Reception
Rev. 1.0, 09/02, page xxiv of xxxiv