Scs Pin Control And Arbitration; Figure 16.9 Example Of Simultaneous Transmission/Reception Flowchart - Hitachi H8S/2628 Hardware Manual

H8s/2628 series 16-bit single-chip microcomputer
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[1]
Initialization
Transmission/reception started
(TE = 1, RE = 1)
[2]
Read TDRE in SSSR.
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
Read SSSR
ORER = 1?
[4]
No
RDRF = 1?
Read received data in SSRDR
RDRF automatically cleared
Continuous data
transmission/reception
Clear TEND in SSSR to 0
Clear TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.

Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart

SCS Pin Control and Arbitration

SCS
SCS
SCS
16.4.5
When bits CSS1 and CSS0 in SSCRH are specified to B'10, the SCS pin functions as an input to
detect arbitration. The arbitration detection period starts when setting the MSS bit in SSCRH to 1
and ends when starting serial transfer. When a low level signal is input to the SCS pin within the
period, a conflict error occurs. At this time, the CE bit in SSSR is set to 1 and the MSS bit is
cleared to 0.
Rev. 1.0, 09/02, page 424 of 568
Start
No
Yes
No
Yes
[5]
Yes
No
Error processing
[1] Initialization:
Specify the settings such as transmit/receive
data format
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading
and confirming that the TDRE bit is 1. The
TDRE bit is automatically cleared to 0 and
transmission is started by writing data to
SSTDR.
[3] Receive error processing:
When a receive error occurs, execute the
designated error processing after reading the
ORER bit in SSSR. After that, clear the ORER
bit to 0. While the ORER bit is set to 1,
transmission or reception is not resumed.
[4] Check the SSU state and read receibe data:
Read receibe data in SSRDR after reading and
confirming that the RDRF bit is 1. The RDRF bit
is cleared. A change of the RDRF bit (from 0 to 1)
canbe notified by RXI interrupt.
[5] Procedure for continuous data transmission/
reception:
[3]
To continue setial data transmission/reception,
confirm that the TDRE bit 1meaning that SSTDR
is ready to be written to. After that, data can be
written to SSTDR. The TDRE bit is automatically
cleared to 0 by writing data to SSTDR.

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