Figure 15.10 Transmit Message Cancellation Flowchart - Hitachi H8S/2628 Hardware Manual

interrupt mask register (MBIMR) and the mailbox empty interrupt bit (IRR8) in the interrupt mask
register (IMR) are both simultaneously set to enable interrupts, interrupts may be sent to the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission
Figure 15.10 shows a flowchart for transmit message cancellation.
Message transmit wait TXPR setting
Set TXCR bit corresponding to
End of transmission/transmission

Figure 15.10 Transmit Message Cancellation Flowchart

Rev. 1.0, 09/02, page 392 of 568
message to be canceled
Cancellation possible?
Yes
Message not sent
Clear TXCR, TXPR
ABACK = 1
IRR8 = 1
IMR8 = 1?
No
Interrupt to CPU
Clear TXACK
Clear ABACK
Clear IRR8
cancellation
: Settings by user
: Processing by hardware
No
Completion of message transmission
TXACK = 1
Clear TXCR, TXPR
IRR8 = 1
Yes