Medium-Speed Mode - Hitachi H8S/2628 Hardware Manual

• MSTPCRC
Bit Bit Name
7 MSTPC7*
6 MSTPC6*
5 MSTPC5*
4 MSTPC4
3 MSTPC3
2 MSTPC2
1 MSTPC1*
0 MSTPC0*
Note:* MSTPA7 is a readable/writable bit with an initial value of 0. The write value should always
be 0.
MSTPA2, MSTPB6, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, MSTPC1, and MSTPC0
are readable/writable bits with an initial value of 1. The write value should always be 1.
21.2

Medium-Speed Mode

When the SCK0 to SCK2 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK0 to SCK2 bits. Bus masters
(DTC) other than the CPU also operate in medium-speed mode. On-chip peripheral modules other
than bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software
standby mode. When software standby mode is cleared by an external interrupt, medium-speed
mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Initial Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Module
PC break controller (PBC)
Hitachi Controller Area Network (HCAN)
Synchronous serial communication unit (SSU)
Rev. 1.0, 09/02, page 483 of 568