Hitachi H8S/2628 Hardware Manual page 34

Table 10.30 PWM Output Registers and Output Pins (cont) .................................................... 211
Table 10.31 Phase Counting Mode Clock Input Pins ............................................................... 214
Table 10.32 Up/Down-Count Conditions in Phase Counting Mode 1...................................... 215
Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 2...................................... 216
Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 3...................................... 217
Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 4...................................... 218
Table 10.36 TPU Interrupts ...................................................................................................... 222
Section 11 8-Bit Timers
Table 11.1 Pin Configuration.................................................................................................. 243
Table 11.2 8-Bit Timer Interrupt Sources ............................................................................... 257
Table 11.3 Timer Output Priorities ......................................................................................... 260
Table 11.4 Switching of Internal Clock and TCNT Operation ............................................... 261
Section 12 Programmable Pulse Generator (PPG)
Table 12.1 Pin Configuration.................................................................................................. 265
Section 13 Watchdog Timer
Table 13.1 WDT Interrupt Source .......................................................................................... 288
Section 14 Serial Communication Interface (SCI)
Table 14.1 Pin Configuration.................................................................................................. 293
Table 14.2 The Relationships between The N Setting in BRR and Bit Rate B ...................... 308
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ........................... 309
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ........................... 310
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ........................... 311
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 311
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 312
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 313
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 313
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372) ..................................................................................... 314
Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372) ..................................................................................................... 314
Table 14.10 Serial Transfer Formats (Asynchronous Mode).................................................... 316
Table 14.11 SSR Status Flags and Receive Data Handling ...................................................... 323
Table 14.12 SCI Interrupt Sources............................................................................................ 351
Table 14.13 SCI Interrupt Sources............................................................................................ 352
Section 15 Hitachi Controller Area Network (HCAN)
Table 15.1 HCAN Pins ........................................................................................................... 357
Table 15.2 Limits for the Settable Value ................................................................................ 387
Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR..................................................... 388
Rev. 1.0, 09/02, page xxxii of xxxiv