Hitachi H8S/2628 Hardware Manual page 19

16.3.1 SS Control Register H (SSCRH)..........................................................................407
16.3.2 SS Control Register L (SSCRL) ..........................................................................409
16.3.3 SS Mode Register (SSMR) ..................................................................................410
16.3.4 SS Enable Register (SSER)..................................................................................411
16.3.5 SS Status Register (SSSR) ...................................................................................412
16.3.6 SS Transmit Data Register 0 to 3 (SSTDR0 to SSTDR3) ...................................415
16.3.7 SS Receive Data Register 0 to 3 (SSRDR0 to SSRDR3).....................................415
16.3.8 SS Shift Register (SSTRSR) ................................................................................415
16.4 Operation...........................................................................................................................416
16.4.1 Transfer Clock .....................................................................................................416
16.4.2 Relationship of Clock Phase, Polarity, and Data..................................................416
16.4.3 Relationship between Data I/O Pins and the Shift Register .................................416
16.4.4 Data Transmission and Data Reception ...............................................................417
16.4.5 SCS Pin Control and Arbitration..........................................................................424
16.5 Interrupt Requests .............................................................................................................425
16.6 Usage Note........................................................................................................................426
16.6.1 Setting of Module Stop Mode..............................................................................426
Section 17 A/D Converter................................................................................. 427
17.1 Features .............................................................................................................................427
17.2 Input/Output Pins ..............................................................................................................429
17.3 Register Description..........................................................................................................430
17.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................430
17.3.2 A/D Control/Status Register (ADCSR) ...............................................................431
17.3.3 A/D Control Register (ADCR) ............................................................................433
17.4 Operation...........................................................................................................................434
17.4.1 Single Mode.........................................................................................................434
17.4.2 Scan Mode ...........................................................................................................434
17.4.3 Input Sampling and A/D Conversion Time..........................................................435
17.4.4 External Trigger Input Timing .............................................................................437
17.5 Interrupt Source.................................................................................................................437
17.6 A/D Conversion Accuracy Definitions .............................................................................438
17.7 Usage Notes ......................................................................................................................440
17.7.1 Module Stop Mode Setting ..................................................................................440
17.7.2 Permissible Signal Source Impedance .................................................................440
17.7.3 Influences on Absolute Accuracy ........................................................................440
17.7.4 Range of Analog Power Supply and Other Pin Settings ......................................441
17.7.5 Notes on Board Design ........................................................................................441
17.7.6 Notes on Noise Countermeasures ........................................................................441
Section 18 RAM ............................................................................................... 443
Section 19 ROM ............................................................................................... 445
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