φ
TCLKA to TCLKD
SCK0 to SCK2
TxD0 to TxD2
(transmit data)
RxD0 to RxD2
(receive data)
Figure 23.11 SCI Input/Output Timing (Clocked Synchronous Mode)
φ
Figure 23.12 A/D Converter External Trigger Input Timing
Rev. 1.0, 09/02, page 556 of 568
t
TCKWL
Figure 23.9 TPU Clock Input Timing
SCK0 to SCK2
Figure 23.10 SCK Clock Input Timing
t
TXD
t
TCKS
t
t
t
SCKW
SCKr
SCKf
t
Scyc
t
t
RXS
RXH
t
TRGS
t
TCKS
t
TCKWH