Interrupt Sources; Table 15.4 Hcan Interrupt Sources - Hitachi H8S/2628 Hardware Manual

15.5

Interrupt Sources

Table 15.4 lists the HCAN interrupt sources. These sources can be masked except the reset
processing interrupt by power-on reset (IRR0). Masking is implemented using the mailbox
interrupt mask register (MBIMR), interrupt mask register (IMR), and IRQ enable register (IER).
For details on the interrupt vector of each interrupt source, refer to section 5, Interrupt Controller.

Table 15.4 HCAN Interrupt Sources

Name Description
Error passive interrupt (TEC ≥ 128 or REC ≥ 128)
ERS0/OVR0
Bus off interrupt (TEC ≥ 256)
Reset processing interrupt by power-on reset
Remote frame reception
Error warning interrupt (TEC ≥ 96)
Error warning interrupt (REC ≥ 96)
Overload frame transmission interrupt
Unread message overwrite
Detection of CAN bus operation in HCAN sleep mode
RM0 Mailbox 0 message reception
RM1 Mailbox 1-15 message reception
SLE0 Message transmission/cancellation
IRQ2 Setting the RxDIE bit in HCANMON to 1 generates an
IRQ2 interrupt caused by an HRxD input signal.
Rev. 1.0, 09/02, page 400 of 568
Interrupt DTC
Flag Activation
IRR5 Not
possible
IRR6
IRR0
IRR2
IRR3
IRR4
IRR7
IRR9
IRR12
IRR1 Possible
IRR1 Not
possible
IRR8 Not
possible
IRQ2F Possible