Conflict Between Timer Counter (Tcnt) Write And Increment; Figure 13.3 Writing To Tcnt, Tcsr, And Rstcsr (Example For Wdt0); Figure 13.4 Conflict Between Tcnt Write And Increment - Hitachi H8S/2628 Hardware Manual

Figure 13.3 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)

Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as
other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for
RSTCSR.
13.5.2

Conflict between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 13.4 shows this operation.
φ
Address
Internal write signal
TCNT input clock
TCNT

Figure 13.4 Conflict between TCNT Write and Increment

TCNT write
Writing to RSTE and RSTS bits
15
Address:
H'FF74
H'FF76
TCSR write
Writing 0 to WOVF bit
15
Address:
H'FF74
H'FF76
TCNT write cycle
T 1
8 7
H'5A Write data
8 7
H'5A Write data or H'00
T 2
N
Counter write data
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