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Figure 16.1 Block Diagram of SSU............................................................................................ 406
Figure 16.2 Relationship of Clock Phase, Polarity, and Data ..................................................... 416
Figure 16.3 Relationship between Data I/O Pins and the Shift Register .................................... 417
Figure 16.4 Example of SSU Initialization................................................................................. 418
Figure 16.5 Example of Transmission Operation ....................................................................... 419
Figure 16.6 Example of Data Transmission Flowchart .............................................................. 420
Figure 16.7 Example of Reception Operation ............................................................................ 422
Figure 16.8 Example of Data Reception Flowchart.................................................................... 423
Figure 16.9 Example of Simultaneous Transmission/Reception Flowchart ............................... 424
Figure 16.10 Arbitration Detection Timing (Before Transfer) ................................................... 425
Figure 16.11 Arbitration Detection Timing (After Transfer End) ................................................ 425
Section 17 A/D Converter
Figure 17.1 Block Diagram of A/D Converter ........................................................................... 428
Figure 17.2 A/D Conversion Timing .......................................................................................... 435
Figure 17.3 External Trigger Input Timing ................................................................................ 437
Figure 17.4 A/D Conversion Accuracy Definitions.................................................................... 439
Figure 17.5 A/D Conversion Accuracy Definitions.................................................................... 439
Figure 17.6 Example of Analog Input Circuit ............................................................................ 440
Figure 17.7 Example of Analog Input Protection Circuit ........................................................... 442
Figure 17.8 Analog Input Pin Equivalent Circuit ....................................................................... 442
Section 19 ROM
Figure 19.1 Block Diagram of Flash Memory............................................................................ 446
Figure 19.2 Flash Memory State Transitions.............................................................................. 447
Figure 19.3 Boot Mode............................................................................................................... 448
Figure 19.4 User Program Mode ................................................................................................ 449
Figure 19.5 Flash Memory Block Configuration........................................................................ 450
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 458
Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 459
Figure 19.8 Example of RAM Overlap Operation...................................................................... 460
Figure 19.9 Program/Program-Verify Flowchart........................................................................ 462
Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 464
Section 20 Clock Pulse Generator
Figure 20.1 Block Diagram of Clock Pulse Generator ............................................................... 467
Figure 20.2 Connection of Crystal Resonator (Example) ........................................................... 470
Figure 20.3 Crystal Resonator Equivalent Circuit ...................................................................... 470
Figure 20.4 External Clock Input (Examples) ............................................................................ 471
Figure 20.5 External Clock Input Timing................................................................................... 472
Figure 20.6 Note on Board Design of Oscillator Circuit ............................................................ 474
Figure 20.7 External Circuitry Recommended for PLL Circuit.................................................. 475
Rev. 1.0, 09/02, page xxvi of xxxiv
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