Interrupt Requests; Figure 16.10 Arbitration Detection Timing (Before Transfer); Figure 16.11 Arbitration Detection Timing (After Transfer End) - Hitachi H8S/2628 Hardware Manual

Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
External input to
Internal-clocked
MSS
Transfer start
Data written
CE
to SSTDR
Hi-Z
output
Arbitration detection Worst time for
period internally clocking SCS

Figure 16.10 Arbitration Detection Timing (Before Transfer)

φ
(Hi-Z)
MSS
Transfer
start
Transfer
CE
end
Arbitration detection period

Figure 16.11 Arbitration Detection Timing (After Transfer End)

16.5

Interrupt Requests

The SSU interrupt requests consist of transmit data register empty, transmit end, receive data
register full, overrun error, and conflict error. Of these interrupt sources, transmit data register
empty, transmit end, receive data register full can activate the DTC for data transfer.
Rev. 1.0, 09/02, page 425 of 568