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16.2
Input/Output Pins
Table 16.1 shows the SSU pin configuration.
Table 16.1 Pin Configuration
Name
SSU clock
SSU receive data input
SSU transmit data output
SSU chip select input/output
16.3
Register Descriptions
The SSU has the following registers.
• SS control register H (SSCRH)
• SS control register L (SSCRL)
• SS mode register (SSMR)
• SS enable register (SSER)
• SS status register (SSSR)
• SS transmit data register 0 to 3 (SSTDR0 to SSTDR3)
• SS receive data register 0 to 3 (SSRDR0 to SSRDR3)
16.3.1
SS Control Register H (SSCRH)
SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value
selection, SSCK pin selection, and SCS pin selection.
Bit
Bit Name
7
MSS
Symbol
SSCK
SSI
SSO
SCS
Initial Value
R/W
0
R/W
I/O
Function
I/O
SSU clock input/output
I/O
SSU receive data input/output
I/O
SSU transmit data input/output
I/O
SSU chip select input/output
Description
Master/Slave Device Selection
Selects that this module is used in master mode
or slave mode. When master mode is selected,
transfer clocks are output from the SSCK pin.
When the CE bit in SSSR is set, this bit is
automatically cleared.
0: Slave mode is selected.
1: Master mode is selected.
Rev. 1.0, 09/02, page 407 of 568
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