Figure 5.1 Block Diagram Of Interrupt Controller - Hitachi H8S/2628 Hardware Manual

A block diagram of the interrupt controller is shown in figure 5.1.
SYSCR
NMI input
IRQ input
Internal interrupt request
SWDTEND to SSERT_i1
Legend
: IRQ sense control register
ISCR
: IRQ enable register
IER
: IRQ status register
ISR
: Interrupt priority register
IPR
: System control register
SYSCR
Rev. 1.0, 09/02, page 64 of 568
INTM1, INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
Interrupt controller

Figure 5.1 Block Diagram of Interrupt Controller

Interrupt
request
Vector number
Priority
determination
IPR
CPU
I
CCR
I2 to I0
EXR