Hitachi H8S/2628 Hardware Manual page 340

Bit Bit Name
1 MPB
0 MPBT
• Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit Bit Name
7 TDRE
6 RDRF
Rev. 1.0, 09/02, page 304 of 568
Initial Value R/W
0 R
0 R/W
Initial Value R/W
1 R/W
0 R/W
Description
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit data.
Description
Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR
and data can be written to TDR
[Clearing conditions]
•
When 0 is written to TDRE after reading TDRE
= 1
•
When the DTC is activated by a TXI interrupt
request and writes data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF
= 1
•
When the DTC is activated by an RXI interrupt
and transferred data from RDR
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.