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16.3.3
SS Mode Register (SSMR)
SSMR selects the MSB first/LSB first, clock phase, clock polarity, and clock rate of synchronous
serial communication.
Bit
Bit Name
7
MLS
6
CPOS
5
CPHS
4, 3
2
CKS2
1
CKS1
0
CKS0
Rev. 1.0, 09/02, page 410 of 568
Initial Value
R/W
0
R/W
0
R/W
0
R/W
All 0
0
R/W
0
R/W
0
R/W
Description
MSB First/LSB First
Selects the serial data is transmitted in MSB first
or LSB first.
0: LSB first
1: MSB first
Clock Polarity Selection
Selects SSCK clock polarity.
0: High output in idle mode, and low output in
active mode
1: Low output in idle mode, and high output in
active mode
Clock Phase Selection
Selects SSCK clock phase.
0: Data changes at the first edge.
1: Data is latched at the first edge.
Reserved
The write value should always be 0.
Transfer Clock Rate Selection
Select the transfer clock rate (prescaler division
rate) when an internal clock is selected.
000: φ/2
001: φ/4
010: φ/8
011: φ/16
100: φ/32
101: φ/64
110: φ/128
111: φ/256
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