Table 10.25 Tiorl_3 (Channel 3) - Hitachi H8S/2628 Hardware Manual

Table 10.25 TIORL_3 (Channel 3)

Bit 3 Bit 2 Bit 1
IOC3 IOC2 IOC1
0 0 0
1
1 0
1
1 0 0
1
1 X
Legend
X: Don't care
Note:* When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Description
Bit 0 TGRC_3
IOC0 Function
0 Output
compare
1
register*
0
1
0
1
0
1
0 Input
capture
register*
1
X
X
TIOCC3 Pin Function
Output disabled
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Capture input source is the TIOCC3 pin
Input capture at rising edge
Capture input source is the TIOCC3 pin
Input capture at falling edge
Capture input source is the TIOCC3 pin
Input capture at both edges
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down
Rev. 1.0, 09/02, page 187 of 568