Table of Contents
Advertisement
φ φ φ φ Clock Output Disabling Function
21.7
The output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for
the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus
cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When
DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is
set. Table 21.4 shows the state of the φ pin in each processing state.
Table 21.4 φ φ φ φ Pin State in Each Processing State
Register Settings
DDR
PSTOP
0
X
1
0
1
1
21.8
Usage Notes
21.8.1
I/O Port Status
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
consumption for the output current when a high-level signal is output.
21.8.2
Current Consumption during Oscillation Stabilization Wait Period
Current consumption increases during the oscillation settling wait period.
21.8.3
DTC Module Stop
Depending on the operating status of the DTC, MSTPA6 bit may not be set to 1. Setting of the
DTC module stop mode should be carried out only when the respective module is not activated.
For details, refer to section 8, Data Transfer Controller (DTC).
21.8.4
On-Chip Peripheral Module Interrupt
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
Rev. 1.0, 09/02, page 490 of 568
Normal Mode
Sleep Mode
High impedance
High impedance
φ output
φ output
Fixed high
Fixed high
Software
Hardware
Standby Mode
Standby Mode
High impedance
High impedance
Fixed high
High impedance
Fixed high
High impedance
Advertisement
Table of Contents
