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15.8.3
HCAN Sleep Mode
The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set even
in sleep mode.
15.8.4
Interrupts
When the mailbox interrupt mask register (MBIMR) is set, the interrupt registers (IRR8, 2, 1) are
not set by reception completion, transmission completion, or transmission cancellation of the set
mailboxes.
15.8.5
Error Counters
In the case of error active and error passive, REC and TEC perform count up and down normally.
In the bus-off state, 11-bit recessive sequences are counted (REC + 1) using REC. When REC
reaches 96 during the count, IRR4 and GSR1 are set.
15.8.6
Register Access
Byte or word access can be performed for all HCAN registers. Longword access should be
avoided.
15.8.7
HCAN Medium-Speed Mode
In medium-speed mode, the HCAN registers cannot be read/written.
15.8.8
Register Hold in Standby Modes
All HCAN registers are initialized in hardware standby mode and software standby mode.
15.8.9
Use on Bit Manipulation Instructions
Since the HCAN status flag is cleared by writing 1, do not use the bit manipulation instructions to
clear the flag. To clear the flag, use the MOV instructions and write 1 only to the bit to be cleared.
Rev. 1.0, 09/02, page 403 of 568
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