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8.2.2
DTC Mode Register B (MRB)
MRB is an 8-bit register that selects the DTC operating mode.
Bit
Bit Name
Initial Value
7
CHNE
Undefined
6
DISEL
Undefined
5 to
Undefined
0
8.2.3
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
8.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
R/W
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to 8.5.4, Chain Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the interrupt source flag, and clearing of DTCER,
are not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after the end of a data transfer.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
Reserved
These bits have no effect on DTC operation. Only 0
should be written to these bits.
Rev. 1.0, 09/02, page 101 of 568
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