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1.1
Overview
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
• Various peripheral functions
PC break controller
Data transfer controller
16-bit timer-pulse unit (TPU)
8-bit timer (TMR)
Programmable pulse generator (PPG)
Watchdog timer
Asynchronous or clocked synchronous serial communication interface (SCI)
Hitachi controller area network (HCAN)
Synchronous serial communication unit (SSU)
10-bit A/D converter
Clock pulse generator
• On-chip memory
ROM
Model
F-ZTAT Version
HD64F2628
Masked ROM
HD6432628
Version
HD6432627
• General I/O ports
I/O pins: 59
Input-only pins: 17
• Supports various power-down states
• Compact package
Package
QFP-100
Section 1 Overview
ROM
128 kbytes
128 kbytes
96 kbytes
(Code)
FP-100M
RAM
8 kbytes
8 kbytes
6 kbytes
Body Size
×
14.0
14.0 mm
Rev. 1.0, 09/02, page 1 of 568
Remarks
Under development
Under development
Pin Pitch
0.5 mm
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