Low-Power Control Register (Lpwrcr) - Hitachi H8S/2628 Hardware Manual

Bit Bit Name
2 SCK2
1 SCK1
0 SCK0
Legend
X: Don't care
20.1.2

Low-Power Control Register (LPWRCR)

Bit Bit Name

7 to
4

3, 2
1 STC1
0 STC0
Initial Value R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W

All 0
All 0 R/W
0 R/W
0 R/W
Description
System Clock Select 0 to 2
These bits select the bus master clock.
000: High-speed mode
001: Medium-speed clock is φ/2
010: Medium-speed clock is φ/4
011: Medium-speed clock is φ/8
100: Medium-speed clock is φ/16
101: Medium-speed clock is φ/32
11X: Setting prohibited
Description
Reserved
The write value should always be 0.
Reserved
These bits can be read from and write to, but
should not be set to 1.
Frequency Multiplication Factor
The STC bits specify the frequency multiplication
factor of the PLL circuit.
00: ×1
01: ×2
10: ×4
11: Setting prohibited
Rev. 1.0, 09/02, page 469 of 568