Hitachi H8S/2628 Hardware Manual page 24

Figure 6.2 Operation in Power-Down Mode Transitions.............................................................. 89
Section 7 Bus Controller
Figure 7.1 On-Chip Memory Access Cycle.................................................................................. 93
Figure 7.2 On-Chip Support Module Access Cycle...................................................................... 94
Figure 7.3 On-Chip HCAN Module Access Cycle (with Wait States) ......................................... 94
Figure.7.4 On-chip SSU Module Access Cycle............................................................................ 95
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC ............................................................................................... 98
Figure 8.2 Block Diagram of DTC Activation Source Control .................................................. 104
Figure 8.3 Location of DTC Register Information in Address Space......................................... 105
Figure 8.4 Flowchart of DTC Operation..................................................................................... 108
Figure 8.5 Memory Mapping in Normal Mode .......................................................................... 109
Figure 8.6 Memory Mapping in Repeat Mode ........................................................................... 110
Figure 8.7 Memory Mapping in Block Transfer Mode............................................................... 111
Figure 8.8 Chain Transfer Operation .......................................................................................... 112
Figure 8.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)...................... 113
Figure 8.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) ..................................... 114
Figure 8.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 114
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU............................................................................................ 162
Figure 10.2 Example of Counter Operation Setting Procedure .................................................. 197
Figure 10.3 Free-Running Counter Operation ............................................................................ 198
Figure 10.4 Periodic Counter Operation..................................................................................... 199
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 199
Figure 10.6 Example of 0 Output/1 Output Operation ............................................................... 200
Figure 10.7 Example of Toggle Output Operation ..................................................................... 200
Figure 10.8 Example of Input Capture Operation Setting Procedure ......................................... 201
Figure 10.9 Example of Input Capture Operation....................................................................... 202
Figure 10.10 Example of Synchronous Operation Setting Procedure ........................................ 203
Figure 10.11 Example of Synchronous Operation...................................................................... 204
Figure 10.12 Compare Match Buffer Operation ......................................................................... 205
Figure 10.13 Input Capture Buffer Operation............................................................................. 205
Figure 10.14 Example of Buffer Operation Setting Procedure................................................... 206
Figure 10.15 Example of Buffer Operation (1)........................................................................... 206
Figure 10.16 Example of Buffer Operation (2)........................................................................... 207
Figure 10.17 Cascaded Operation Setting Procedure ................................................................. 208
Figure 10.18 Example of Cascaded Operation (1)...................................................................... 209
Figure 10.19 Example of Cascaded Operation (2)...................................................................... 209
Figure 10.20 Example of PWM Mode Setting Procedure .......................................................... 211
Rev. 1.0, 09/02, page xxii of xxxiv