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Timing of Recovery from Hardware Standby Mode
Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a
power-on reset.
Figure 21.5 Timing of Recovery from Hardware Standby Mode
21.6
Module Stop Mode
21.6.1
Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI*, HCAN, and A/D converter are retained.
After reset clearance, all modules other than DTC are in module stop mode.
When an on-chip peripheral module is in module stop mode, read/write access to its registers is
disabled.
Note: The internal states of some SCI registers are retained.
t
t≥100ns
OSC1
Rev. 1.0, 09/02, page 489 of 568
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