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Table 10.30 PWM Output Registers and Output Pins (cont)
Channel
4
5
Note:* In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode
setting procedure.
Select counter clock
Select counter clearing source
Select waveform output level
Set PWM mode
<PWM mode>
Figure 10.20 Example of PWM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers
are used as the duty cycle levels.
Registers
TGR4A_4
TGR4B_4
TGRA_5
TGRB_5
PWM mode
[1]
[2]
[3]
Set TGR
[4]
[5]
Start count
[6]
PWM Mode 1
TIOCA4
TIOCA5
[1]
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
[2]
Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
[3]
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4]
Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
[5]
Select the PWM mode with bits MD3 to MD0 in
TMDR.
[6]
Set the CST bit in TSTR to 1 start the count
operation.
Rev. 1.0, 09/02, page 211 of 568
Output Pins
PWM Mode 2
TIOCA4
TIOCB4
TIOCA5
TIOCB5
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