Reset, Interrupt, And System Control Registers And Control Bits; Interrupt Pin Request Status And Control Register (Irqsc) - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
5.8

Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to Table 4-2 and
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, "Modes of
5.8.1

Interrupt Pin Request Status and Control Register (IRQSC)

This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
7
R 0
W
Reset 0
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Field
6 Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
IRQPDD pull-up/pull-down device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
5 Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
IRQEDG levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When IRQEDG = 1 and the internal pull device is enabled, the
pull-up device is reconfigured as an optional pull-down device.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4 IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
IRQPE be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3 IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
IRQF 0 No IRQ request.
1 IRQ event detected.
98
Table 4-3 in Chapter 4,
Operation."
6 5
IRQPDD IRQEDG
0 0
Table 5-3. IRQSC Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
"Memory," of this data sheet for the absolute address
4 3
IRQF
IRQPE
0 0
IRQ was Power On Reset ENABLED on old MC68HC908GP32
Description
2 1
0
IRQIE
IRQACK
0 0
Freescale Semiconductor
0
IRQMOD
0