ROHS MC9S08QE128 Reference Manual page 97

Out of reset, all peripheral clocks will be enabled. For lowest possible run or wait currents, user software
should disable the clock source to any peripheral not in use. The actual clock will be enabled or disabled
immediately following the write to the Clock Gating Control registers (SCGC1 and SCGC2). Any
peripheral with a gated clock can not be used unless its clock is enabled. Writing to the registers of a
peripheral with a disabled clock has no effect.
User software should disable the peripheral before disabling the clocks to
the peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in SCGC1 and
SCGC2.
Freescale Semiconductor
NOTE
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 5 Resets, Interrupts, and General System Control
97