Interrupt Stack Frame; External Interrupt Request (Irq) Pin - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first
(see Table 5-2).
5.5.1

Interrupt Stack Frame

Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of
the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning
from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is
generated by this same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2

External Interrupt Request (IRQ) Pin

External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ pin (if
enabled) can wake the MCU.
92
UNSTACKING
ORDER
7
5 1
CONDITION CODE REGISTER
4 2
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
3 3
2 4 PROGRAM COUNTER HIGH
1 5
PROGRAM COUNTER LOW
STACKING
ORDER
* High byte (H) of index register is not automatically stacked.
Figure 5-1. Interrupt Stack Frame
MC9S08QE128 MCU Series Reference Manual, Rev. 2
TOWARD LOWER ADDRESSES
0
SP AFTER
INTERRUPT STACKING
*
SP BEFORE
THE INTERRUPT
TOWARD HIGHER ADDRESSES
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