Development Support; Introduction; Forcing Active Background; Dbg Clock Gating - ROHS MC9S08QE128 Reference Manual

Chapter 17

Development Support

17.1

Introduction

Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip flash and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins. Debug is done
through commands fed into the target MCU via the single-wire background debug interface. The debug
module provides a means to selectively trigger and capture bus information so an external development
system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external
access to the address and data signals.
17.1.1

Forcing Active Background

The method for forcing active background mode depends on the specific HCS08 derivative. For the
MC9S08QE128 Series, you can force active background after a power-on reset by holding the BKGD pin
low as the device exits the reset condition. You can also force active background by driving BKGD low
immediately after a serial background command that writes a one to the BDFR bit in the SBDFR register.
Other causes of reset including an external pin reset or an internally generated error reset ignore the state
of the BKGD pin and reset into normal user mode. If no debug pod is connected to the BKGD pin, the
MCU will always reset into normal operating mode.
17.1.2

DBG Clock Gating

The bus clock to the DBG can be gated on and off using the DBG bit in SCGC2. This bit is set after any
reset, which enables the bus clock to this module. To conserve power, the DBG bit can be cleared to disable
the clock to this module when not in use. See
17.1.3 Module Configuration
The alternate BDC clock source is the ICSLCLK. This clock source is selected by clearing the CLKSW
bit in the BDCSCR register. For details on ICSLCLK, see the "Functional Description" section of the ICS
chapter.
Freescale Semiconductor
Section 5.7, "Peripheral Clock Gating,"
MC9S08QE128 MCU Series Reference Manual, Rev. 2
for details.
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