System Power Management Status And Control 3 Register (Spmsc3) - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
Field
3 Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
PPDF 0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
2 Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
PPDACK
1 Partial Power-Down Enable — The write-once PPDE bit can be used to disable the partial power-down feature.
PPDE 0 Partial power-down is disabled
1 Partial power-down is enabled and controlled by the PPDC bit.
0 Partial Power Down Control — The PPDC bit controls which power down mode is selected. This bit cannot be
PPDC set if LPR = 1. If PPDC and LPR are set in a single write instruction, only PPDC will actually be set. PPDE must
be set in order for PPDC to be set. There are restrictions on LVDE and LVDSE. See
0 Stop3 low power mode enabled.
1 Stop2 partial power down mode enabled.
5.8.9 System Power Management Status and Control 3 Register
(SPMSC3)
This high page register is used to report the status of the low voltage warning function and to select the low
voltage detect trip voltage.
7
R LVWF
W
1
POR: 0
Stop2
u
Wakeup
1
LVR: 0
Any
1
other 0
reset:
= Unimplemented or Reserved
Figure 5-11. System Power Management Status and Control 3 Register (SPMSC3)
1
LVWF will be set in the case when V
Field
7 Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
LVWF 0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6 Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status. Writing a 1 to
LVWACK LVWACK clears LVWF to a 0 if a low voltage warning is not present.
106
Table 5-11. SPMSC2 Register Field Descriptions (continued)
6 5
0
LVDV
LVWACK
0 0
0 u
0 u
0 u
transitions below the trip point or after reset and V
Supply
Table 5-12. SPMSC3 Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
LVWV LVWIE
0 0
u u
u 0
u 0
Description
Table 3-1 for details.
2 1
0 0
0 0
0 0
0 0
0 0
u = Unaffected by reset
is already below V
Supply
Freescale Semiconductor
0
0
0
0
0
0
.
LVW