Port E Registers - ROHS MC9S08QE128 Reference Manual

Field
7:0 Internal Pull Enable for Port D Bits — Each of these control bits determines if the internal pull-up or pull-down
PTDPE[7:0] device is enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port D bit n.
1 Internal pull-up/pull-down device enabled for port D bit n.
6.5.4.4 Port D Slew Rate Enable Register (PTDSE)
7
R
PTDSE7
W
Reset: 0
Field
7:0 Output Slew Rate Enable for Port D Bits — Each of these control bits determines if the output slew rate control
PTDSE[7:0] is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
6.5.4.5 Port D Drive Strength Selection Register (PTDDS)
7
R
PTDDS7
W
Reset: 0
Figure 6-25. Drive Strength Selection for Port D Register (PTDDS)
Field
7:0 Output Drive Strength Selection for Port D Bits — Each of these control bits selects between low and high
PTDDS[7:0] output drive for the associated PTD pin. For port D pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port D bit n.
1 High output drive strength selected for port D bit n.
6.5.5

Port E Registers

Port E is controlled by the registers listed below.
Freescale Semiconductor
Table 6-21. PTDPE Register Field Descriptions
6 5
PTDSE6 PTDSE5
0 0
Figure 6-24. Slew Rate Enable for Port D Register (PTDSE)
Table 6-22. PTDSE Register Field Descriptions
6 5
PTDDS6 PTDDS5
0 0
Table 6-23. PTDDS Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
PTDSE4 PTDSE3
0 0
Description
4 3
PTDDS4 PTDDS3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTDSE2 PTDSE1
0 0
2 1
PTDDS2 PTDDS1
0 0
0
PTDSE0
0
0
PTDDS0
0
125