Spi Baud Rate Register (Spixbr) - ROHS MC9S08QE128 Reference Manual

Field
4 Master Mode-Fault Function Enable — When the SPI is configured for slave mode, this bit has no meaning or
MODFEN effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used (refer
to Table 15-2
0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
3 Bidirectional Mode Output Enable — When bidirectional mode is enabled by SPI pin control 0 (SPC0) = 1,
BIDIROE BIDIROE determines whether the SPI data output driver is enabled to the single bidirectional SPI I/O pin.
Depending on whether the SPI is configured as a master or a slave, it uses either the MOSI (MOMI) or MISO
(SISO) pin, respectively, as the single SPI data I/O pin. When SPC0 = 0, BIDIROE has no meaning or effect.
0 Output driver disabled so SPI data I/O pin acts as an input
1 SPI I/O pin enabled as an output
1 SPI Stop in Wait Mode
SPISWAI 0 SPI clocks continue to operate in wait mode
1 SPI clocks stop when the MCU enters wait mode
0 SPI Pin Control 0 — The SPC0 bit chooses single-wire bidirectional mode. If MSTR = 0 (slave mode), the SPI
SPC0 uses the MISO (SISO) pin for bidirectional SPI data transfers. If MSTR = 1 (master mode), the SPI uses the
MOSI (MOMI) pin for bidirectional SPI data transfers. When SPC0 = 1, BIDIROE is used to enable or disable the
output driver for the single bidirectional SPI I/O pin.
0 SPI uses separate pins for data input and data output
1 SPI configured for single-wire bidirectional operation
15.4.3

SPI Baud Rate Register (SPIxBR)

This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
7
R 0
W
Reset 0
= Unimplemented or Reserved
Field
6:4 SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
SPPR[2:0] as shown in
drives the input of the SPI baud rate divider (see
2:0 SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
SPR[2:0] Table 15-6. The input to this divider comes from the SPI baud rate prescaler (see
divider is the SPI bit rate clock for master mode.
Freescale Semiconductor
Table 15-3. SPIxC2 Register Field Descriptions
for more details).
6 5
SPPR2 SPPR1
0 0
Figure 15-7. SPI Baud Rate Register (SPIxBR)
Table 15-4. SPIxBR Register Field Descriptions
Table 15-5. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
4 3
0
SPPR0
0 0
Description
Figure 15-4).
Serial Peripheral Interface (S08SPIV3)
2 1
SPR2 SPR1
0 0
Figure 15-4). The output of this
0
SPR0
0
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