Analog Comparator 3V (Acmpvlpv1); Introduction; Acmp Configuration Information; Acmp/Tpm Configuration Information - ROHS MC9S08QE128 Reference Manual

Chapter 9

Analog Comparator 3V (ACMPVLPV1)

9.1

Introduction

MC9S08QE128 Series MCUs have two independent analog comparators (ACMPs), named ACMP1 and
ACMP2.
The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for
comparing one analog input voltage to an internal reference voltage. The comparator circuit is designed to
operate across the full range of the supply voltage (rail-to-rail operation).
Figure 9-1 shows the MC9S08QE128 Series block diagram with the ACMP highlighted.
Ignore any references to stop1 low-power mode in this chapter, because the
MC9S08QE128 device does not support it.
9.1.1 ACMP Configuration Information
When using the bandgap reference voltage for input to ACMP1+ and/or ACMP2+, the user must enable
the bandgap buffer by setting SPMS[BGBE]. For value of bandgap voltage reference see the data sheet.
9.1.2 ACMP/TPM Configuration Information
The ACMP modules can be configured to connect the output of the analog comparator to a TPM input
capture channel 0 by setting the corresponding ACICx bit in SOPT2. With ACICx set, the TPMxCH0 pin
is not available externally regardless of the configuration of the TPMx module.
The ACMP1 output can be connected to TPM1CH0; The ACMP2 output can be connected to TPM2CH0.
9.1.3

ACMP Clock Gating

The bus clock to both of the ACMPs can be gated on and off using the SCGC2[ACMP] bit. This bit is set
after any reset, which enables the bus clock to this module. To conserve power, the ACMP bit can be
cleared to disable the clock to this module when not in use. See
for details.
Freescale Semiconductor
NOTE
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Section 5.7, "Peripheral Clock Gating,"
167