ROHS MC9S08QE128 Reference Manual page 290

Timer/PWM Module (S08TPMV3)
When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not =
0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM,
and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the
TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced
low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is
forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the
channel value register matches the timer counter.
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL
290
1
... 0
TPMxCHn
CHnF BIT
TOF BIT
Figure 16-3. High-True Pulse of an Edge-Aligned PWM
1
... 0
TPMxCHn
CHnF BIT
TOF BIT
Figure 16-4. Low-True Pulse of an Edge-Aligned PWM
MC9S08QE128 MCU Series Reference Manual, Rev. 2
2 6
3 4 5 7 8
2 3 4 5 6 7 8
0 1 2 ...
0 1 2 ...
Freescale Semiconductor