Port A Registers - ROHS MC9S08QE128 Reference Manual

6.5.1

Port A Registers

Port A is controlled by the registers listed below.
The pins PTA4 and PTA5 are unique. PTA4 is an output only, so the control bits for the input functions
will not have any effect on this pin. PTA5 is an input only, so the control bits for the output functions will
not have any effect on this pin.
6.5.1.1 Port A Data Register (PTAD)
7
R
PTAD7
W
Reset: 0
1
Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.
Field
7:0 Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
PTAD[7:0] pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
6.5.1.2 Port A Data Direction Register (PTADD)
7
R
PTADD7
W
Reset: 0
1
PTADD5 has no effect on the input-only PTA5 pin.
2
PTADD4 has no effect on the output-only PTA4 pin.
Field
7:0 Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTADD[7:0] PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Freescale Semiconductor
Inconsistent treatment of symbology: PTA4 AND PTAD4, for example
6 5
PTAD5
PTAD6
0 0
Figure 6-3. Port A Data Register (PTAD)
Table 6-1. PTAD Register Field Descriptions
6 5
1
PTADD6 PTADD5
0 0
Figure 6-4. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
1
PTAD4 PTAD3
0 0
Description
4 3
2
PTADD4 PTADD3
0 0
Description
Chapter 6 Parallel Input/Output Control
2 1
PTAD2 PTAD1
0 0
2 1
PTADD2 PTADD1
0 0
0
PTAD0
0
0
PTADD0
0
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