Tpm Counter Modulo Registers (Tpmxmodh:tpmxmodl) - ROHS MC9S08QE128 Reference Manual

Timer/PWM Module (S08TPMV3)
7
R Bit 7
W
Reset 0
When BDM is active, the timer counter is frozen (this is the value that will be read by user); the coherency
mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became
active, even if one or both counter halves are read while BDM is active. This assures that if the user was
in the middle of reading a 16-bit register when BDM became active, it will read the appropriate value from
the other half of the 16-bit value after returning to normal execution.
16.3.3

TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock, and
the overflow flag (TOF) becomes set. Writing to TPMxMODH or TPMxMODL inhibits the TOF bit and
overflow interrupts until the other byte is written. Reset sets the TPM counter modulo registers to 0x0000
which results in a free running timer counter (modulo disabled).
Writing to either byte (TPMxMODH or TPMxMODL) latches the value into a buffer and the registers are
updated with the value of their write buffer according to the value of CLKSB:CLKSA bits, so:
• If (CLKSB:CLKSA = 0:0), then the registers are updated when the second byte is written
• If (CLKSB:CLKSA not = 0:0), then the registers are updated after both bytes were written, and the
TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If
the TPM counter is a free-running counter, the update is made when the TPM counter changes from
0xFFFE to 0xFFFF
The latching mechanism may be manually reset by writing to the TPMxSC address (whether BDM is
active or not).
When BDM is active, the coherency mechanism is frozen such that the buffer latches remain in the state
they were in when the BDM became active, even if one or both halves of the modulo register are written
while BDM is active. Any write to the modulo registers bypasses the buffer latches and directly writes to
the modulo register while BDM is active.
7
R
Bit 15
W
Reset 0
Figure 16-10. TPM Counter Modulo Register High (TPMxMODH)
294
6 5
6 5
Any write to TPMxCNTL clears the 16-bit counter
0 0
Figure 16-9. TPM Counter Register Low (TPMxCNTL)
6 5
14 13
0 0
MC9S08QE128 MCU Series Reference Manual, Rev. 2
4 3
4 3
0 0
4 3
12 11
0 0
2 1
2 1
0 0
2 1
10 9
0 0
Freescale Semiconductor
0
Bit 0
0
0
Bit 8
0