System Clock Gating Control 2 Register (Scgc2) - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
Field
7 TPM3 Clock Gate Control — This bit controls the clock gate to the TPM3 module.
TPM3 0 Bus clock to the TPM3 module is disabled.
1 Bus clock to the TPM3 module is enabled.
6 TPM2 Clock Gate Control — This bit controls the clock gate to the TPM2 module.
TPM2 0 Bus clock to the TPM2 module is disabled.
1 Bus clock to the TPM2 module is enabled.
5 TPM1 Clock Gate Control — This bit controls the clock gate to the TPM1 module.
TPM1 0 Bus clock to the TPM1 module is disabled.
1 Bus clock to the TPM1 module is enabled.
4 ADC Clock Gate Control — This bit controls the clock gate to the ADC module.
ADC 0 Bus clock to the ADC module is disabled.
1 Bus clock to the ADC module is enabled.
3 IIC2 Clock Gate Control — This bit controls the clock gate to the IIC2 module.
IIC2 0 Bus clock to the IIC2 module is disabled.
1 Bus clock to the IIC2 module is enabled.
2 IIC1 Clock Gate Control — This bit controls the clock gate to the IIC1 module.
IIC1 0 Bus clock to the IIC1 module is disabled.
1 Bus clock to the IIC1 module is enabled.
1 SCI2 Clock Gate Control — This bit controls the clock gate to the SCI2 module.
SCI2 0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module is enabled.
0 SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module.
SCI1 0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module is enabled.
5.8.11

System Clock Gating Control 2 Register (SCGC2)

This high page register contains control bits to enable or disable the bus clock to the RTC and SPIx
modules. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait currents.
See Section 5.7, "Peripheral Clock
User software should disable the peripheral before disabling the clocks to
the peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
7
R
DBG
W
Reset: 1
= Unimplemented or Reserved
Figure 5-13. System Clock Gating Control 2 Register (SCGC2)
108
Table 5-14. SCGC1 Register Field Descriptions
Gating," for more information.
6 5
FLS IRQ
1 1
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
NOTE
4 3
KBI ACMP
1 1
2 1
RTC SPI2
1 1
Freescale Semiconductor
0
SPI1
1