ROHS MC9S08QE128 Reference Manual page 94

Chapter 5 Resets, Interrupts, and General System Control
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
MC9S08QE128 MCU Series Reference Manual, Rev. 2
94 Freescale Semiconductor