Timer/Pulse-Width Modulator (S08Tpmv3); Introduction; Acmp/Tpm Configuration Information; Tpm Clock Gating - ROHS MC9S08QE128 Reference Manual

Chapter 16

Timer/Pulse-Width Modulator (S08TPMV3)

16.1

Introduction

Figure 16-1 shows the MC9S08QE128 Series block diagram with the TPM highlighted.
16.1.1 ACMP/TPM Configuration Information
The ACMP modules can be configured to connect the output of the analog comparator to a TPM input
capture channel 0 by setting the corresponding SOPT2[ACICx] bit. With ACICx set, the TPMxCH0 pin is
not available externally regardless of the configuration of the TPMx module.
The ACMP1 output can be connected to TPM1CH0; The ACMP2 output can be connected to TPM2CH0.
16.1.2

TPM Clock Gating

The bus clock to TPM1, TPM2, and TPM3 can be gated on and off using the SCGC1[TPMx] bits. These
bits are set after any reset, which enables the bus clock to this module. To conserve power, these bits can
be cleared to disable the clock to any of these modules when not in use. See
Gating," for details.
16.1.3

Interrupt Vector

See Section 4.2, "Reset and Interrupt Vector
Freescale Semiconductor
Assignments," for the TPM interrupt vector assignments.
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Section 5.7, "Peripheral Clock
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