ROHS MC9S08QE128 Reference Manual page 211

Table 11-6. ICS Status and Control Register Field Descriptions (continued)
Field
3-2 Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don't update
CLKST immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Output of FLL is selected.
01 FLL Bypassed, Internal reference clock is selected.
10 FLL Bypassed, External reference clock is selected.
11 Reserved.
1 OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
OSCINIT or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
0 ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
FTRIM Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
DRS DMX32
00
01
10
11
1
The resulting bus clock frequency should not exceed the maximum specified bus
clock frequency of the device.
r
Freescale Semiconductor
Table 11-7. DCO frequency range
Reference range
0 31.25 - 39.0625 kHz
1 32.768 kHz
0 31.25 - 39.0625 kHz
1 32.768 kHz
0 31.25 - 39.0625 kHz
1 32.768 kHz
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
1
FLL factor
512
608
1024
1216
1536
1824
Reserved
Internal Clock Source (S08ICSV3)
DCO range
16 - 20 Mhz
19.92 Mhz
32 - 40 Mhz
39.85 Mhz
48 - 60 Mhz
59.77 Mhz
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