System Options Register 2 (Sopt2) - ROHS MC9S08QE128 Reference Manual

Chapter 5 Resets, Interrupts, and General System Control
Field
1 Background Debug Mode Pin Enable — This write-once bit when set enables the PTA4/ACMPO/BKGD/MS
BKGDPE pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA4/ACMPO/BKGD/MS pin functions as PTA4 or ACMPO.
1 PTA4/ACMPO/BKGD/MS pin functions as BKGD/MS.
0 RESET Pin Enable — This write-once bit when set enables the PTA5/IRQ/TCLK/RESET pin to function as
RSTPE RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to the PTA5
function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ or TCLK.
1 PTA5/IRQ/TCLK/RESET pin functions as RESET.
5.8.5

System Options Register 2 (SOPT2)

This high page register contains bits to configure MCU specific features on the MC9S08QE128 Series
devices.
7
R
1
COPCLKS
W
Reset: 0
= Unimplemented or Reserved
1
This bit can be written only one time after reset. Additional writes are ignored.
Field
7 COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
COPCLKS 0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
3 SPI1 Pin Select — This bit selects the location of the MOSI1, MISO1, SPSCLK1, and SS1 pins of the SPI1
SPI1PS module.
0 SPSCLK1 on PTB2, MOSI1 on PTB3, MISO1 on PTB4, and SS1 on PTB5.
1 SPSCLK1 on PTE0, MOSI1 on PTE1, MISO1 on PTE2, and SS1 on PTE3.
2 Analog Comparator 2 to Input Capture Enable — This bit connects the output of ACMP2 to TPM2 input
ACIC2 channel 0. See
Modulator (S08TPMV3)," for more details on this feature.
0 ACMP2 output not connected to TPM2 input channel 0.
1 ACMP2 output connected to TPM2 input channel 0.
102
Table 5-6. SOPT1 Register Field Descriptions (continued)
6 5
0 0
0 0
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Chapter 9, "Analog Comparator 3V
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Description
This is Power ON Reset Default
4 3
0
SPI1PS
0 0
Description
(ACMPVLPV1)," and
2 1
ACIC2 IIC1PS
0 0
Chapter 16, "Timer/Pulse-Width
Freescale Semiconductor
0
ACIC1
0