ROHS MC9S08QE128 Reference Manual page 165

Bit-Manipulation Branch
INH Inherent REL Relative
IMM Immediate IX Indexed, No Offset
DIR Direct IX1 Indexed, 8-Bit Offset
EXT Extended IX2 Indexed, 16-Bit Offset
DD DIR to DIR IMD IMM to DIR
IX+D IX+ to DIR DIX+ DIR to IX+
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
Freescale Semiconductor
Table 8-3. Opcode Map (Sheet 2 of 2)
Read-Modify-Write
9E60 6
NEG
3 SP1
9E61 6
CBEQ
4 SP1
9E63 6
COM
3 SP1
9E64 6
LSR
3 SP1
9E66 6
ROR
3 SP1
9E67 6
ASR
3 SP1
9E68 6
LSL
3 SP1
9E69 6
ROL
3 SP1
9E6A 6
DEC
3 SP1
9E6B 8
DBNZ
4 SP1
9E6C 6
INC
3 SP1
9E6D 5
TST
3 SP1
9E6F 6
CLR
3 SP1
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 8 Central Processor Unit (S08CPUV4)
Control
9EAE 5 9EBE 6
LDHX LDHX
2 IX 4 IX2
Prebyte (9E) and Opcode in
Hexadecimal
Number of Bytes
Register/Memory
9ED0 5 9EE0 4
SUB SUB
4 SP2 3 SP1
9ED1 5 9EE1 4
CMP CMP
4 SP2 3 SP1
9ED2 5 9EE2 4
SBC SBC
4 SP2 3 SP1
9ED3 5 9EE3 4 9EF3
CPX CPX CPHX
4 SP2 3 SP1 3
9ED4 5 9EE4 4
AND AND
4 SP2 3 SP1
9ED5 5 9EE5 4
BIT BIT
4 SP2 3 SP1
9ED6 5 9EE6 4
LDA LDA
4 SP2 3 SP1
9EE7 4
9ED7 5
STA STA
4 SP2 3 SP1
9ED8 5 9EE8 4
EOR EOR
4 SP2 3 SP1
9ED9 5 9EE9 4
ADC ADC
4 SP2 3 SP1
9EDA 5 9EEA 4
ORA ORA
4 SP2 3 SP1
9EDB 5 9EEB 4
ADD ADD
4 SP2 3 SP1
9ECE 5 9EDE 5 9EEE 4 9EFE
LDHX LDX LDX LDHX
3 IX1 4 SP2 3 SP1 3
9EDF 5 9EEF 4 9EFF
STX STX STHX
4 SP2 3 SP1 3
9E60 6 HCS08 Cycles
NEG Instruction Mnemonic
Addressing Mode
3 SP1
165
6
SP1
5
SP1
5
SP1