ROHS MC9S08QE128 Reference Manual page 193

digital value of the analog signal. The result of the conversion is transferred to ADCRH and ADCRL upon
completion of the conversion algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f frequency, precise sample time for continuous conversions cannot be guaranteed when long
ADCK
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in
Conversion Type
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Single or first continuous 8-bit
Single or first continuous 10-bit or 12-bit
Subsequent continuous 8-bit;
> f
f
BUS ADCK
Subsequent continuous 10-bit or 12-bit;
> f
f
BUS ADCK
Subsequent continuous 8-bit;
> f
f
BUS ADCK
Subsequent continuous 10-bit or 12-bit;
> f
f
BUS ADCK
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
Conversion time =
The ADCK frequency must be between f
maximum to meet ADC specifications.
Freescale Semiconductor
frequency, precise sample time for continuous conversions
ADCK
Table 10-12. Total Conversion Time vs. Control Conditions
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
/11
/11
23 ADCK cyc
8 MHz/1
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
MC9S08QE128 MCU Series Reference Manual, Rev. 2
12-bit Analog-to-Digital Converter (S08ADCV1)
ADLSMP
0
0
1
1
11 0
11 0
11 1
11 1
xx 0
xx 0
xx 1
xx 1
5 bus cyc
+
8 MHz
NOTE
minimum and f
ADCK
Table 10-12.
Max Total Conversion Time
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
= 3.5 μs
ADCK
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