Active Bdm Enabled In Stop Mode; Lvd Enabled In Stop Mode; Stop Modes In Low Power Run Mode - ROHS MC9S08QE128 Reference Manual

Mode of Operation
RUN mode
LPRUN mode
WAIT mode - (Assumes WAIT instruction executed.)
LPWAIT mode - (Assumes WAIT instruction executed.)
STOP3 - (Assumes STOPE bit is set and STOP
instruction executed.) Note that STOP3 is used in
place of STOP2 if the BDM or LVD is enabled.
STOP2 - (Assumes STOPE bit is set and STOP
instruction executed.) If BDM or LVD is enabled,
STOP3 will be invoked rather than STOP2.
1
ENBDM is located in the BDC status and control register (BDCSCR) which is write accessible only through BDC commands, see
Support."
2
Configured within the ICS module based on the settings of IREFSTEN, EFRESTEN, IRCLKEN, and ERCLKEN.
3
In stop2, CPU, flash, ICS and all peripheral modules are powered down except for the RTC.
Table 3-2. Power Mode Selections
BDCSCR SPMSC1 SPMSC2
BDM PMC
1
ENBDM LVDE LVDSE LPR
0 x x 0
1 1 1
1 x x x
0 0 x 1
1 0
0 x x 0
1 1 1
1 x x x
0 0 x 1
1 0
0 0 x x
0 1 0 x
0 1 1 x
1 x x x
0 0 x 0
1 0
PMC
CPU & Periph CLKs
PPDC
x on. ICS in any mode.
0 low freq required. ICS in
FBELP mode only.
x CPU clock is off;
peripheral clocks on. ICS
state same as RUN mode.
0 CPU clock is off;
peripheral clocks
at low speed. ICS in
FBELP mode.
0 ICS in STOP. LPO,
OSCOUT, ICSERCLK and
0
ICSIRCLK optionally on
x
x ICSLCLK still active.
1 LPO and OSCOUT
2,3
optionally on
Effects on Sub-System
Voltage
BDM Clock
Regulator
off on
on
off standby
off on
on
off standby
off standby
off
2
off on - stop
currents will
on
be increased
off partial
powerdown
Chapter 17, "Development