System Clock Distribution - ROHS MC9S08QE128 Reference Manual

Chapter 1 Device Overview
LPOCLK
1 kHZ
LPO
ICSERCLK
ICSIRCLK
ICS
ICSFFCLK
ICSOUT
ICSLCLK
OSCOUT
XOSC
CPU
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
EXTAL XTAL
of the bus clock frequency.
24
TPM1CLK
TPM1
COP
RTC
FFCLK*
÷
2
SYNC*
BUSCLK
÷
2
BDC DBG
Figure 1-2. System Clock Distribution Diagram
MC9S08QE128 MCU Series Reference Manual, Rev. 2
TPM2CLK TPM3CLK
TPM2 TPM3
IIC2
IIC1
ADC
ADC has min and max
frequency requirements.
See the ADC chapter
and data sheet for
details.
SCI1 SCI2 SPI1
FLASH SPI2
Flash has frequency
requirements for program
and erase operation. See
the data sheet for details.
Freescale Semiconductor