ROHS MC9S08QE128 Reference Manual page 109

Field
7 DBG Clock Gate Control — This bit controls the bus clock gate to the DBG module.
DBG 0 Bus clock to the DBG module is disabled.
1 Bus clock to the DBG module is enabled.
6 Flash Register Clock Gate Control — This bit controls the bus clock gate to the flash registers. This bit does
FLS not affect normal program execution from with the flash array. Only the clock to the flash control registers is
affected.
0 Bus clock to the flash registers is disabled.
1 Bus clock to the flash registers is enabled.
5 IRQ Clock Gate Control — This bit controls the bus clock gate to the IRQ module.
IRQ 0 Bus clock to the IRQ module is disabled.
1 Bus clock to the IRQ module is enabled.
4 KBI Clock Gate Control — This bit controls the clock gate to both of the KBI modules.
KBI 0 Bus clock to the KBI modules is disabled.
1 Bus clock to the KBI modules is enabled.
3 ACMP Clock Gate Control — This bit controls the clock gate to both of the ACMP modules.
ACMP 0 Bus clock to the ACMP modules is disabled.
1 Bus clock to the ACMP modules is enabled.
2 RTC Clock Gate Control — This bit controls the bus clock gate to the RTC module. Only ICSIRCLK is gated,
RTC OSCOUT and LPOCLK are still available to the RTC.
0 ICSIRCLK to the RTC module is disabled.
1 ICSIRCLK to the RTC module is enabled.
1 SPI2 Clock Gate Control — This bit controls the clock gate to the SPI2 module.
SPI2 0 Bus clock to the SPI2 module is disabled.
1 Bus clock to the SPI2 module is enabled.
0 SPI1 Clock Gate Control — This bit controls the clock gate to the SPI1 module.
SPI1 0 Bus clock to the SPI1 module is disabled.
1 Bus clock to the SPI1 module is enabled.
Freescale Semiconductor
Table 5-15. SCGC2 Register Field Descriptions
MC9S08QE128 MCU Series Reference Manual, Rev. 2
Chapter 5 Resets, Interrupts, and General System Control
Description
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