Functional Description; Operational Modes - ROHS MC9S08QE128 Reference Manual

Internal Clock Source (S08ICSV3)
11.4

Functional Description

11.4.1

Operational Modes

FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=10
BDM Disabled
and LP=1
Entered from any state
when MCU enters stop
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
11.4.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
• CLKS bits are written to 00.
• IREFS bit is written to 1.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to the FLL factor times the internal
reference frequency. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
212
IREFS=0
CLKS=10
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
Figure 11-7. Clock Switching Modes
MC9S08QE128 MCU Series Reference Manual, Rev. 1.11
IREFS=1
CLKS=00
FLL Engaged
Internal (FEI)
FLL Engaged
External (FEE)
IREFS=0
CLKS=00
Stop
IREFS=1
CLKS=01
BDM Enabled
or LP=0
FLL Bypassed
FLL Bypassed
Internal Low
Internal (FBI)
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Freescale Semiconductor